Semiconductor devices are fabricated by forming active devices on or within a semiconductor wafer or workpiece. Hundreds or thousands of integrated circuits or die are typically manufactured on a single workpiece. Typically, a plurality of insulating, conductive, and semiconductive material layers are sequentially deposited and patterned over the workpiece to form the integrated circuits. One of the uppermost-formed material layers typically comprises a layer for bond pads which make electrical connection to the underlying active areas and components within the workpiece. After the integrated circuits are formed on the workpiece, the semiconductor wafer is then singulated into individual die. In most applications, each individual die is then packaged into an integrated circuit package. Integrated circuit packages may be adapted to contain one individual die, or they may be adapted to contain a plurality of individual die, for example, in the case of multi-chip modules.
A prior art packaged integrated circuit 11 is shown in FIG. 1. The packaged integrated circuit 11 includes a package 13 which may comprise plastic or metal, as examples. A plurality of leads 15 are disposed along the sides of the package 13 as shown, although alternatively, the leads 15 may be disposed on the top or the bottom surfaces of the package 13 (not shown). The leads 15 may be arranged in many different types of configurations, as is well known in the art.
An integrated circuit die 17 or semiconductor device is disposed within the package 13. The semiconductor device 17 has a plurality of bond pads 19 disposed on a surface of the semiconductor device 17. To make electrical connection from the bond pads 19 of the semiconductor device to the leads 15, wiring 21 is typically used. The wiring 21 is often referred to in the art as wire bonds, which may be soldered or spot-welded to a bond pad 19 on a semiconductor device 17 at one end, and routed to and bonded to a lead 15 of the integrated circuit package 13 at the other end. The semiconductor device 17 shown in FIG. 1 includes bond pads 19 disposed on a top surface thereof. Alternatively, the bond pads 19 may be disposed on the bottom surface or other areas of the semiconductor device 17. The bond pads 19 may be arranged in a variety of patterns.
FIGS. 2 and 3 are exemplary of two of the several different types of bond pad patterns used in the semiconductor industry.
FIG. 2 shows a top view of a portion of a semiconductor device 100, wherein bond pads 104a and 104b are positioned in a traditional bond pad pattern. The semiconductor device 100 includes a plurality of input/output cells 102a and 102b formed in an upper layer of the semiconductor device 100. The input/output cells 102a and 102b are electrically coupled to active areas within a semiconductor workpiece, not shown. The active areas may reside beneath the input/output cells 102a and 102b, or they may be coupled to the input/output cells 102a and 102b using conductive lines beneath or located to the side of the input/output cells 102a and 102b, for example.
In a traditional bond pad pattern, the bond pads 104a and 104b are staggered and are disposed to the side of the input/output cells 102a and 102b, as shown. The bond pads 104a and 104b are typically coupled to the input/output cells 102a and 102b, respectively, by one or more conductive pins 106a/108a and 106b/108b, respectively. In the prior art semiconductor device 100 shown, there is one bond pad 104a or 104b for each input/output cell 102a and 102b, respectively. Conductive pins 108a and 108b typically are formed in the same interconnect layer that the bond pads 104a and 104b are formed in, while conductive pins 106a and 106b may partially reside in a via layer, for example.
FIG. 3 shows another type of bond pad pattern, referred to in the art as a circuit under pad (CUP) bonding style. In this semiconductor device 120, the bond pads 122a and 122b are disposed directly over an associated input/output cell 102a and 102b, respectively, as shown. Again, one or more conductive pins 124a/126a and 124b/126b may be used to electrically couple each input/output cell 102a and 102b to the bond pads 122a and 122b, respectively.
One problem in the manufacturing and packaging of semiconductor devices is that the semiconductor devices must be selected according to the pattern of the bond pad desired. For example, when designing circuits, a designer must select whether the traditional bond pad style device 100 as shown in FIG. 2 or a CUP bonding pad style device 120 as shown in FIG. 3 will be used in the circuit design. Semiconductor device manufacturers are often required to provide many types of bond style patterns in order to accommodate their customers' needs. This results in increased costs for the semiconductor device manufacturer because of the many different bond pad pattern designs in use in the industry today. Each different bond pad pattern requires a different lithography mask for patterning the bond pads, for example.
Thus, what is needed in the art is a bond pad scheme that gives circuit designers increased choices of bond pad designs, and reduces the number of bond pad patterns that semiconductor device manufacturers are required to manufacture.